Microchip Technology MA330024 Data Sheet
2009-2014 Microchip Technology Inc.
DS70000591F-page 177
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-46:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
—
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
ILR<3:0>: New CPU Interrupt Priority Level bits
1111
= CPU Interrupt Priority Level is 15
•
•
•
0001
•
•
0001
= CPU Interrupt Priority Level is 1
0000
= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111
= Interrupt vector pending is Number 135
•
•
•
0000001
•
•
0000001
= Interrupt vector pending is Number 9
0000000
= Interrupt vector pending is Number 8