Microchip Technology MA330024 Data Sheet
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 18
2009-2014 Microchip Technology Inc.
FIGURE 1-1:
DEVICE BLOCK DIAGRAM
16
OSC1/CLKI
OSC2/CLKO
V
DD
, V
SS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
FRC/LPRC
Oscillators
Regulator
Voltage
V
CAP
IC1-4
I2C1/2
PORTA
Instruction
Decode and
Control
PCH
16
Program Counter
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Address Latch
Program Memory
Data Latch
Lite
ra
l
Dat
a
16
16
16
16
Data Latch
Address
Latch
16
X RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals
to Various Blocks
ADC1
Timers
PORTB
Address Generator Units
1-5
CNx
UART1/2
PWM
9 x 2
PORTC
SPI1,2
OC1-4
Analog
Comparator 1-4
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
present on each device.
ECAN1
QEI1,2
PORTD
PORTE
PORTF
PORTG
DMA
DMA
RAM
Controller
16
16
Data Latch
Address
Latch
Y RAM
PCL
16-Bit ALU