Microchip Technology MA330024 Data Sheet

DS70000591F-page 180

 2009-2014 Microchip Technology Inc.

The DMA Controller features four identical data
transfer channels. Each channel has its own set of
control and status registers. Each DMA channel can be
configured to copy data either from buffers stored in
dual port DMA RAM to peripheral SFRs or from
peripheral SFRs to buffers in DMA RAM. 

The DMA Controller supports the following features:

• Word or byte-sized data transfers.

• Transfers from peripheral to DMA RAM or DMA 

RAM to peripheral

• Indirect Addressing of DMA RAM locations with or 

without automatic post-increment

• Peripheral Indirect Addressing – In some 

peripherals, the DMA RAM read/write addresses 
may be partially derived from the peripheral

• One-Shot Block Transfers – Terminating a DMA 

transfer after one block transfer

• Continuous Block Transfers – Reloading the DMA 

RAM buffer start address after every block 
transfer is complete

• Ping-Pong Mode – Switching between two DMA 

RAM start addresses between successive block 
transfers, thereby filling two buffers alternately

• Automatic or manual initiation of block transfers

For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.

Each DMAC Channel x (x = 0, 1, 2 or 3) contains the
following registers:

• A 16-Bit DMA Channel Control Register 

(DMAxCON)

• A 16-Bit DMA Channel IRQ Select Register 

(DMAxREQ)

• A 16-Bit DMA RAM Primary Start Address Offset 

Register (DMAxSTA)

• A 16-Bit DMA RAM Secondary Start Address 

Offset Register (DMAxSTB)

• A 16-Bit DMA Peripheral Address Register 

(DMAxPAD)

• A 10-Bit DMA Transfer Count Register (DMAxCNT)

An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.

CPU

SRAM

DMA RAM

CPU Peripheral DS Bus

Peripheral 3

DMA

Peripheral

Non-DMA

SRAM X-Bus

Peripheral 1

DMA

Ready

Peripheral 2

DMA

Ready

Ready

Ready

DMA DS Bus

Peripheral Indirect Address

Note: For clarity, CPU and DMA address buses are not shown.

DMA

Cont

rol

DMA

Channels

0

1

2

3