Microchip Technology MA330024 Data Sheet
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 186
2009-2014 Microchip Technology Inc.
REGISTER 8-8:
DMACS1: DMA CONTROLLER STATUS REGISTER 1
U-0
U-0
U-0
U-0
R-1
R-1
R-1
R-1
—
—
—
—
LSTCH3
LSTCH2
LSTCH1
LSTCH0
bit 15
bit 8
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
PPST3
PPST2
PPST1
PPST0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
LSTCH<3:0>: Last DMA Channel Active bits
1111
= No DMA transfer has occurred since system Reset
1110
= Reserved
•
•
•
0100
= Reserved
0011
= Last data transfer was by DMA Channel 3
0010
= Last data transfer was by DMA Channel 2
0001
= Last data transfer was by DMA Channel 1
0000
= Last data transfer was by DMA Channel 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
PPST3: Channel 3 Ping-Pong Mode Status Flag bit
1
= DMA3STB register is selected
0
= DMA3STA register is selected
bit 2
PPST2: Channel 2 Ping-Pong Mode Status Flag bit
1
= DMA2STB register is selected
0
= DMA2STA register is selected
bit 1
PPST1: Channel 1 Ping-Pong Mode Status Flag bit
1
= DMA1STB register is selected
0
= DMA1STA register is selected
bit 0
PPST0: Channel 0 Ping-Pong Mode Status Flag bit
1
= DMA0STB register is selected
0
= DMA0STA register is selected