Microchip Technology MA330024 Data Sheet

Page of 462
 2009-2014 Microchip Technology Inc.
DS70000591F-page 217
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
12.0
TIMER1
The Timer1 module is a 16-bit timer, which can serve
as a time counter for the Real-Time Clock (RTC), or
operate as a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated from the low-power 32.767 kHz 
crystal oscillator available on the device.
• Can be operated in Asynchronous Counter mode 
from an external clock source.
• The external clock input (T1CK) can optionally be 
synchronized to the internal device clock and the 
clock synchronization is performed after the 
prescaler. 
The unique features of Timer1 allow it to be used for
Real-Time Clock (RTC) applications. A block diagram
of Timer1 is shown in 
.
The Timer1 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (F
CY
).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit: TCS (T1CON<1>)
• Timer Synchronization Control bit: TSYNC 
(T1CON<2>)
• Timer Gate Control bit: TGATE (T1CON<6>)
The timer control bit settings for different operating
modes are given in the 
TABLE 12-1:
TIMER MODE SETTINGS
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
 
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Timers” (DS70205) in the
“dsPIC33/PIC24 Family Reference Man-
ual”
, which is available from the Microchip
web site (
www.microchip.com
). The infor-
mation in this data sheet supersedes the
information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
 in
this data sheet for device-specific register
and bit information.
Mode
TCS
TGATE
TSYNC
Timer 
0
0
x
Gated Timer
0
1
x
Synchronous 
Counter
1
x
1
Asynchronous 
Counter
1
x
0
TGATE
TCS
00
10
x1
Comparator
PR1
TGATE
Set T1IF Flag
0
1
TSYNC
1
0
Sync
Equal
Reset
T1CK
Prescaler
(/n)
TCKPS<1:0>
Gate
Sync
F
CY
Falling Edge
Detect
Prescaler
(/n)
TCKPS<1:0>
TMR1