Microchip Technology MA330024 Data Sheet
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 282
2009-2014 Microchip Technology Inc.
REGISTER 20-2:
U
x
STA: UART
x
STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
R/W-0, HC
R/W-0
R-0
R-1
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL1
URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15,13
UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11
= Reserved; do not use
10
= Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01
= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00
= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14
UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1
1
= UxTX Idle state is ‘0’
0
= UxTX Idle state is ‘1’
If IREN = 1:
1
1
= IrDA
®
encoded UxTX Idle state is ‘1’
0
= IrDA encoded UxTX Idle state is ‘0’
bit 12
Unimplemented: Read as ‘0’
bit 11
UTXBRK: UARTx Transmit Break bit
1
= Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop
bit; cleared by hardware upon completion
0
= Sync Break transmission is disabled or has completed
bit 10
UTXEN: UARTx Transmit Enable bit
)
1
= Transmit is enabled, UxTX pin is controlled by UARTx
0
= Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by the port
bit 9
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1
= Transmit buffer is full
0
= Transmit buffer is not full; at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1
= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0
= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11
= Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10
= Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x
= Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1:
Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on
enabling the UART module for transmit operation. That section of the manual is available on the Microchip
web site:
enabling the UART module for transmit operation. That section of the manual is available on the Microchip
web site:
www.microchip.com
.