Microchip Technology MA330024 Data Sheet
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 308
2009-2014 Microchip Technology Inc.
REGISTER 21-26: CxTRmnCON: ECANx TX/RX BUFFER mn CONTROL REGISTER
(m = 0, 2, 4, 6; n = 1, 3, 5, 7)
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENn
TXABTn
TXLARBn
TXERRn
TXREQn
RTRENn
TXnPRI1
TXnPRI0
bit 15
bit 8
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENm
TXABTm
TXLARBm
)
TXERRm
(
)
TXREQm
RTRENm
TXmPRI1
TXmPRI0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
See Definition for bits<7:0>, Controls Buffer n
bit 7
TXENm: TX/RX Buffer Selection bit
1
= Buffer TRBn is a transmit buffer
0
= Buffer TRBn is a receive buffer
bit 6
TXABTm: Message Aborted bit
(
)
1
= Message was aborted
0
= Message completed transmission successfully
bit 5
TXLARBm: Message Lost Arbitration bit
(
)
1
= Message lost arbitration while being sent
0
= Message did not lose arbitration while being sent
bit 4
TXERRm: Error Detected During Transmission bit
1
= A bus error occurred while the message was being sent
0
= A bus error did not occur while the message was being sent
bit 3
TXREQm: Message Send request bit
1
= Requests that a message be sent; the bit automatically clears when the message is successfully sent
0
= Clears the bit to ‘0’; while set, requests a message abort
bit 2
RTRENm: Auto-Remote Transmit Enable bit
1
= When a remote transmit is received, TXREQm will be set
0
= When a remote transmit is received, TXREQm will be unaffected
bit 1-0
TXmPRI<1:0>: Message Transmission Priority bits
11
= Highest message priority
10
= High intermediate message priority
01
= Low intermediate message priority
00
= Lowest message priority
Note 1:
This bit is cleared when TXREQm is set.
Note:
The buffers, SID, EID, DLC, Data Field, and Receive Status registers are located in DMA RAM.