Microchip Technology MA330024 Data Sheet
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 342
2009-2014 Microchip Technology Inc.
REGISTER 22-12: ADCPC6: ADC CONVERT PAIR CONTROL REGISTER 6
(
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQEN12
PEND12
SWTRG12
TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7
IRQEN12: Interrupt Request Enable 12 bit
1
= Enables IRQ generation when requested conversion of Channels AN25 and AN24 is completed
0
= IRQ is not generated
bit 6
PEND12: Pending Conversion Status 12 bit
1
= Conversion of Channels AN25 and AN24 is pending; set when selected trigger is asserted
0
= Conversion is complete
bit 5
SWTRG12: Software Trigger 12 bit
1
= Starts conversion of AN25 (INTREF) and AN24 (EXTREF) if selected by the TRGSRCx<4:0> bits
)
This bit is automatically cleared by hardware when the PEND12 bit is set.
0
= Conversion has not started
Note 1:
The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.
conversions are in progress, the conversion is performed when the conversion resources are available.
2:
This register is not available on dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices.