Microchip Technology TDGL002 - chipKIT Uno32 Development Board TDGL002 TDGL002 Data Sheet
Product codes
TDGL002
© 2011 Microchip Technology Inc.
DS61143H-page 207
PIC32MX3XX/4XX
Revision H (May 2011)
The revision includes the following global update:
• All references to V
DDCORE
/V
CAP
have been
changed to: V
CORE
/V
CAP
• Added references to the new V-Temp temperature
range: -40ºC to +105ºC
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
Major updates are referenced by their respective
section in the following table.
formatting changes throughout the data sheet text.
Major updates are referenced by their respective
section in the following table.
TABLE A-3:
MAJOR SECTION UPDATES
Section Name
Update Description
Updated the V
BUS
.
.
Added Note 2 to the Timer1-5 Register Map (see
).
Updated the All Resets value for I2C1CON<15:0> and I2C2CON<15:0>
in the I2C1 and I2C2 Register Map (see
in the I2C1 and I2C2 Register Map (see
).
Updated the All Resets value for SPI1STAT<15:0> and SPI2STAT<15:0>
in the SPI1 and SPI2 Register Map (see
in the SPI1 and SPI2 Register Map (see
Updated the All Resets value for CM1CON<15:0> and CM2CON<15:0>
in the Comparator Register Map (see
in the Comparator Register Map (see
Renamed the RCDIV<2:0> bits to FRCDIV<2:0> and the LOCK bit to
SLOCK in the OSCCON register, and added Note 3 and the
SYSKEYregister to the System Control Registers Map (see
SLOCK in the OSCCON register, and added Note 3 and the
SYSKEYregister to the System Control Registers Map (see
Updated the All Resets value for the PMSTAT register in the Parallel
Master Port Register Map (see
Master Port Register Map (see
).
Updated the All Resets value for CHECON<15:0> and CHETAG<15:0>
in the Prefetch Register Map (see
in the Prefetch Register Map (see
Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2
register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively in the
Device Configuration Word Summary (see
register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively in the
Device Configuration Word Summary (see
Added Notes 1 through 4 to the USB Register Map (see
).
Added a note on Flash LVD Delay and
Updated the PIC32MX3XX/4XX Family Clock Diagram (see
Updated the PIC32MX3XX/4XX Family USB Interface Diagram (see
Updated the Output Compare Module Block Diagram (see
Updated the ADC Conversion Clock Period Block Diagram (see
Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2
register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively (see
register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively (see
).