Microchip Technology MA330016 Data Sheet

© 2007-2011 Microchip Technology Inc.

DS70290J-page 57

R/SO-0

R/W-0

R/W-0

U-0

U-0

U-0

U-0

U-0

WR

WREN

WRERR

—

—

—

—

—

bit 15

bit 8

U-0

R/W-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

—

ERASE

—

—

NVMOP<3:0>

bit 7

bit 0

SO = Settable Only bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete 

0 = Program or erase operation is complete and inactive

bit 14

WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations

bit 13

WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set 

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12-7

Unimplemented: Read as ‘0’

bit 6

ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4

Unimplemented: Read as ‘0’

bit 3-0

NVMOP<3:0>: NVM Operation Select bits

If ERASE = 1:
1111 = Memory bulk erase operation
1101 = Erase General Segment
1100 = Erase Secure Segment
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erase a single Configuration register byte

If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte

Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP<3:0> bits are unimplemented.