Microchip Technology MA330016 Data Sheet
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DS70290J-page 66
© 2007-2011 Microchip Technology Inc.
FIGURE 6-2:
SYSTEM RESET TIMING
Reset
Run
Device Status
V
DD
V
POR
Vbor
V
BOR
POR
BOR
SYSRST
T
PWRT
T
POR
T
BOR
Oscillator Clock
T
OSCD
T
OST
T
LOCK
Time
FSCM
T
FSCM
1
2
3
4
5
6
Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active
until V
DD
crosses the V
POR
threshold and the delay T
POR
has elapsed.
2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
DD
crosses the
V
BOR
threshold and the delay T
BOR
has elapsed. The delay T
BOR
ensures the voltage regulator output
becomes stable.
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
period of time (T
PWRT
) after a BOR. The delay T
PWRT
ensures that the system power supplies have stabilized
at the appropriate level for full-speed operation. After the delay T
PWRT
has elapsed, the SYSRST becomes
inactive, which in turn enables the selected oscillator to start generating clock cycles.
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
. Refer to
for more information.
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
appropriate start-up routine.
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
is ready and the delay T
FSCM
elapsed.