Microchip Technology MA330016 Data Sheet
© 2007-2011 Microchip Technology Inc.
DS70290J-page 67
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
6.4
Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
V
reset from power-on. The POR circuit is active until
V
DD
crosses the V
POR
threshold and the delay T
POR
has elapsed. The delay T
POR
ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
(RCON<0>) register is set to indicate the Power-on
Reset.
6.4.1
Brown-out Reset (BOR) and
Power-up timer (PWRT)
Power-up timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the V
circuit that resets the device when the V
DD
is too low
(V
DD
< V
BOR
) for proper device operation. The BOR
circuit keeps the device in Reset until V
DD
crosses
V
BOR
threshold and the delay T
BOR
has elapsed. The
delay T
BOR
ensures the voltage regulator output
becomes stable.
The BOR status bit in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
V
The BOR status bit in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
V
DD
should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(T
(T
PWRT
) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (T
operation before the SYSRST is released.
The power-up timer delay (T
PWRT
) is programmed by
the Power-on Reset Timer Value Select bits
(FPWRT<2:0>) in the POR Configuration register
(FPOR<2:0>), which provide eight settings (from 0 ms
to 128 ms). Refer to
(FPWRT<2:0>) in the POR Configuration register
(FPOR<2:0>), which provide eight settings (from 0 ms
to 128 ms). Refer to
for further details.
shows the typical brown-out scenarios. The
reset delay (T
BOR
+ T
PWRT
) is initiated each time V
DD
rises above the V
BOR
trip point
TABLE 6-2:
OSCILLATOR PARAMETERS
Symbol
Parameter
Value
V
POR
POR threshold
1.8V nominal
T
POR
POR extension time
30
μs maximum
V
BOR
BOR threshold
2.5V nominal
T
BOR
BOR extension time
100
μs maximum
T
PWRT
Programmable power-up time delay
0-128 ms nominal
T
FSCM
Fail-Safe Clock Monitor Delay
900
μs maximum
Note:
When the device exits the Reset
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all operating parameters within
specification.
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all operating parameters within
specification.