Microchip Technology MA330011 Data Sheet
dsPIC33F
DS70165E-page 288
Preliminary
©
2007 Microchip Technology Inc.
REGISTER 22-9:
AD1PCFGH: ADC1 PORT CONFIGURATION REGISTER HIGH
(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG31
PCFG30
PCFG29
PCFG28
PCFG27
PCFG26
PCFG25
PCFG24
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG23
PCFG22
PCFG21
PCFG20
PCFG19
PCFG18
PCFG17
PCFG16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
PCFG<31:16>: ADC Port Configuration Control bits
1
= Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AV
SS
0
= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1:
On devices without 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
ports without a corresponding input on device.
2:
ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 port Configuration register exists.
REGISTER 22-10: ADxPCFGL: ADCx PORT CONFIGURATION REGISTER LOW
(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
PCFG<15:0>: ADC Port Configuration Control bits
1
= Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AV
SS
0
= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1:
On devices without 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
ports without a corresponding input on device.
2:
On devices with two analog-to-digital modules, both AD1PCFGL and AD2PCFGL will affect the
configuration of port pins multiplexed with AN0-AN15.
configuration of port pins multiplexed with AN0-AN15.