Microchip Technology MA330011 Data Sheet
©
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 289
dsPIC33F
23.0
SPECIAL FEATURES
dsPIC33F devices include several features intended to
maximize application flexibility and reliability, and mini-
mize cost through elimination of external components.
These are:
maximize application flexibility and reliability, and mini-
mize cost through elimination of external components.
These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
23.1
Configuration Bits
The Configuration bits can be programmed (read as
‘
‘
0
’), or left unprogrammed (read as ‘
1
’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 23-1.
Table 23-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and
FICD Configuration registers are shown in Table 23-2.
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and
FICD Configuration registers are shown in Table 23-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only be
accessed using table reads and table writes.
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only be
accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘
should always be ‘
1111 1111
’. This makes them
appear to be
NOP
instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘
Configuration bits are not implemented in the
corresponding locations, writing ‘
1
’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
TABLE 23-1:
DEVICE CONFIGURATION REGISTER MAP
Note:
This data sheet summarizes the features
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
of this group of dsPIC33F devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC30F
Family Reference Manual” (DS70046).
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0xF80000
FBS
RBS<1:0>
—
—
BSS<2:0>
BWRP
0xF80002
FSS
RSS<1:0>
—
—
SSS<2:0>
SWRP
0xF8004
FGS
—
—
—
—
—
GSS1
GSS0
GWRP
0xF8006
FOSCSEL
IESO
—
TEMP
—
0xF8008
FOSC
FCKSM<1:0>
—
—
—
OSCIOFNC
POSCMD<1:0>
0xF800A
FWDT
FWDTEN
WINDIS
—
WDTPRE
WDTPOST<3:0>
0xF800C
FPOR
PWMPIN
(1)
HPOL
(1)
LPOL
(1)
—
—
FPWRT<2:0>
0xF800E
RESERVED3
Reserved
(2)
0xF8010
FUID0
User Unit ID Byte 0
0xF8012
FUID1
User Unit ID Byte 1
0xF8014
FUID2
User Unit ID Byte 2
0xF8016
FUID3
User Unit ID Byte 3
Note
1:
On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX), these bits are reserved (read as ‘
1
’ and
must be programmed as ‘
1
’).
2:
These reserved bits read as ‘
1
’ and must be programmed as ‘
1
’.
3:
Unimplemented bits are read as ‘
0
’.
4:
This reserved bit is a read-only copy of the GCP bit.