Microchip Technology MA330011 Data Sheet
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66
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TABLE 3-31:
PORTG REGISTER MAP
(1)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISG
02E4
TRISG15
TRISG14
TRISG13
TRISG12
—
—
TRISG9
TRISG8
TRISG7
TRISG6
—
—
TRISG3
TRISG2
TRISG1
TRISG0
F3CF
PORTG
02E6
RG15
RG14
RG13
RG12
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
RG1
RG0
xxxx
LATG
02E8
LATG15
LATG14
LATG13
LATG12
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1
LATG0
xxxx
ODCG
06E4
ODCG15
ODCG14
ODCG13
ODCG12
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
ODCG3
ODCG2
ODCG1
ODCG0
xxxx
Legend:
x
= unknown value on Reset, — = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal for 100-pin devices.
Note
1:
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 3-32:
SYSTEM CONTROL REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RCON
0740
TRAPR
IOPUWR
—
—
—
—
—
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
xxxx
(1)
OSCCON
0742
—
COSC<2:0>
—
NOSC<2:0>
CLKLOCK
—
LOCK
—
CF
—
LPOSCEN
OSWEN
0300
(2)
CLKDIV
0744
ROI
DOZE<2:0>
DOZEN
FRCDIV<2:0>
PLLPOST<1:0>
—
PLLPRE<4::0>
0040
PLLFBD
0746
—
—
—
—
—
—
—
PLLDIV<8:0>
0030
OSCTUN
0748
—
—
—
—
—
—
—
—
—
—
TUN<5:0>
0000
Legend:
x
= unknown value on Reset, — = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note
1:
RCON register Reset values dependent on type of Reset.
2:
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 3-33:
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
ERASE
—
—
NVMOP<3:0>
0000
(1)
NVMKEY
0766
—
—
—
—
—
—
—
—
NVMKEY<7:0>
0000
Legend:
x
= unknown value on Reset, — = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note
1:
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 3-34:
PMD REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0770
T5MD
T4MD
T3MD
T2MD
T1MD
QEIMD
PWMMD
DCIMD
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
C2MD
C1MD
AD1MD
0000
PMD2
0772
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0774
T9MD
T8MD
T7MD
T6MD
—
—
—
—
—
—
—
—
—
—
I2C2MD
AD2MD
0000
Legend:
x
= unknown value on Reset, — = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.