Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 108
© 2011-2014 Microchip Technology Inc.
REGISTER 9-4:
DCRCCON: DMA CRC CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
—
—
BYTO<1:0>
WBO
(1)
—
—
BITO
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
PLEN<4:0>
7:0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
CRCEN
CRCAPP
(1)
CRCTYP
—
—
CRCCH<2:0>
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits
bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits
11
= Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
per half-word)
10
= Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
half-word)
01
= Endian byte swap on word boundaries (i.e., reverse source byte order)
00
= No swapping (i.e., source byte order)
bit 27
WBO:
CRC Write Byte Order Selection bit
(1)
1
= Source data is written to the destination re-ordered as defined by BYTO<1:0>
0
= Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24
bit 24
BITO:
CRC Bit Order Selection bit
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1
= The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0
= The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1
= The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0
= The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8
bit 12-8
PLEN<4:0>:
Polynomial Length bits
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
These bits are unused.
These bits are unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
Denotes the length of the polynomial – 1.
bit 7
CRCEN:
CRC Enable bit
1
= CRC module is enabled and channel transfers are routed through the CRC module
0
= CRC module is disabled and channel transfers proceed normally
Note 1:
When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.