Microchip Technology TDGL019 User Manuals

Table of Contents

• TABLE 1: PIC32MX1XX General Purpose Family Features

  2
• TABLE 2: PIC32MX2XX USB Family Features

  3
• 32-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

  1
  • 1.0 Device Overview

    19
    • FIGURE 1-1: Block Diagram

      19
    • TABLE 1-1: Pinout I/O Descriptions

      20
  • 2.0 Guidelines for Getting Started with 32-bit MCUs

    27
    • 2.1 Basic Connection Requirements

      27
    • 2.2 Decoupling Capacitors

      27
      • FIGURE 2-1: Recommended Minimum Connection

        28
    • 2.3 Capacitor on Internal Voltage Regulator (Vcap)

      28
    • 2.4 Master Clear (MCLR) Pin

      28
      • FIGURE 2-2: MCLR Pin Connections

        28
    • 2.5 ICSP Pins

      28
    • 2.6 JTAG

      29
    • 2.7 External Oscillator Pins

      29
      • FIGURE 2-3: Suggested Oscillator Circuit Placement

        29
    • 2.8 Unused I/Os

      29
    • 2.9 Sosc Design Recommendation

      29
      • FIGURE 2-4: Recommended Oscillator Circuit Placement

        29
    • 2.10 Typical Application Connection Examples

      30
      • FIGURE 2-5: Capacitive Touch Sensing With Graphics Application

        30
      • FIGURE 2-6: Audio Playback Application

        30
  • 3.0 CPU

    31
    • 3.1 Features

      31
      • FIGURE 3-1: MIPS32® M4K® Processor Core Block Diagram

        31
    • 3.2 Architecture Overview

      32
      • Table 3-1: MIPS32® M4K® processor core High-Performance Integer Multiply/Divide Unit Latencies and Repeat Rates

        32
      • Table 3-2: Coprocessor 0 Registers

        33
      • Table 3-3: MIPS32® M4K® processor core Exception Types

        34
    • 3.3 Power Management

      34
    • 3.4 EJTAG Debug Support

      34
  • 4.0 Memory Organization

    35
    • 4.1 PIC32MX1XX/2XX Memory Layout

      35
      • FIGURE 4-1: Memory Map on Reset for PIC32MX110/210 Devices (4 KB RAM, 16 KB Flash)

        36
      • FIGURE 4-2: Memory Map on Reset for PIC32MX120/220 Devices (8 KB RAM, 32 KB Flash)

        37
      • FIGURE 4-3: Memory Map on Reset for PIC32MX130/230 Devices (16 KB RAM, 64 KB Flash)

        38
      • FIGURE 4-4: Memory Map on Reset for PIC32MX150/250 Devices (32 KB RAM, 128 KB Flash)

        39
      • FIGURE 4-5: Memory Map on Reset for PIC32MX170/270 Devices (64 KB RAM, 256 KB Flash)

        40
    • 4.2 Special Function Registers

      41
      • TABLE 4-1: Bus Matrix Register Map

        41
      • TABLE 4-2: Interrupt Register Map (Continued)

        42
      • TABLE 4-3: Timer1-Timer5 Register Map

        44
      • TABLE 4-4: Input Capture 1-Input Capture 5 Register Map

        45
      • TABLE 4-5: Output Compare 1-Output Compare 5 Register Map

        46
      • TABLE 4-6: I2C1 and I2C2 Register Map

        47
      • TABLE 4-7: UART1 and UART2 Register Map

        48
      • Table 4-8: SPI1 and SPI2 Register Map

        49
      • TABLE 4-9: ADC Register Map (Continued)

        50
      • TABLE 4-10: DMA Global Register Map

        52
      • TABLE 4-11: DMA CRC Register Map

        52
      • TABLE 4-12: DMA Channels 0-3 Register Map (Continued)

        53
      • TABLE 4-13: Comparator Register Map

        56
      • TABLE 4-14: Comparator Voltage Reference Register Map

        56
      • TABLE 4-15: Flash Controller Register Map

        57
      • TABLE 4-16: System Control Register Map

        58
      • TABLE 4-17: DEVCFG: Device Configuration Word Summary

        59
      • TABLE 4-18: Device and Revision ID Summary

        59
      • TABLE 4-19: PortA Register Map

        60
      • TABLE 4-20: PORTB Register Map

        61
      • TABLE 4-21: PORTC Register Map

        62
      • Table 4-22: Peripheral Pin Select Input Register Map (Continued)

        63
      • Table 4-23: Peripheral Pin Select Output Register Map

        65
      • TABLE 4-24: Parallel Master Port Register Map

        68
      • TABLE 4-25: RTCC Register Map

        69
      • TABLE 4-26: CTMU Register Map

        69
      • TABLE 4-27: USB Register Map (Continued)

        70
    • 4.3 Control Registers

      73
      • Register 4-1: BMXCON: Bus Matrix Configuration Register

        73
      • Register 4-2: BMXDKPBA: Data RAM Kernel Program Base Address Register

        74
      • Register 4-3: BMXDUDBA: Data RAM User Data Base Address Register

        75
      • Register 4-4: BMXDUPBA: Data RAM User Program Base Address Register

        76
      • Register 4-5: BMXDRMSZ: Data RAM Size Register

        77
      • Register 4-6: BMXPUPBA: Program Flash (PFM) User Program Base Address Register

        77
      • Register 4-7: BMXPFMSZ: Program Flash (PFM) Size Register

        78
      • Register 4-8: BMXBOOTSZ: Boot Flash (IFM) Size Register

        78
  • 5.0 Flash Program Memory

    79
    • Register 5-1: NVMCON: Programming Control Register

      80
    • Register 5-2: NVMKEY: Programming Unlock Register

      81
    • Register 5-3: NVMADDR: Flash Address Register

      81
    • Register 5-4: NVMDATA: Flash Program Data Register

      82
    • Register 5-5: NVMSRCADDR: Source Data Address Register

      82
  • 6.0 Resets

    83
    • FIGURE 6-1: System Reset Block Diagram

      83
    • Register 6-1: RCON: Reset Control Register

      84
    • Register 6-2: RSWRST: Software Reset Register

      85
  • 7.0 Interrupt Controller

    87
    • FIGURE 7-1: Interrupt Controller Module Block Diagram

      87
    • Table 7-1: Interrupt IRQ, Vector and Bit Location

      88
    • Register 7-1: INTCON: Interrupt Control Register

      90
    • Register 7-2: INTSTAT: Interrupt Status Register

      91
    • Register 7-3: IPTMR: Interrupt Proximity Timer Register

      91
    • Register 7-4: IFSx: Interrupt Flag Status Register

      92
    • Register 7-5: IECx: Interrupt Enable Control Register

      92
    • Register 7-6: IPCx: Interrupt Priority Control Register

      93
  • 8.0 Oscillator Configuration

    95
    • FIGURE 8-1: Oscillator Diagram

      96
    • Register 8-1: OSCCON: Oscillator Control Register

      97
    • Register 8-2: OSCTUN: FRC Tuning Register

      100
    • Register 8-3: REFOCON: Reference Oscillator Control Register

      101
    • Register 8-4: REFOTRIM: Reference Oscillator Trim Register

      103
  • 9.0 Direct Memory Access (DMA) Controller

    105
    • FIGURE 9-1: DMA Block Diagram

      105
    • Register 9-1: DMACON: DMA Controller Control Register

      106
    • Register 9-2: DMASTAT: DMA Status Register

      107
    • Register 9-3: DMAADDR: DMA Address Register

      107
    • Register 9-4: DCRCCON: DMA CRC Control Register (Continued)

      108
    • Register 9-5: DCRCDATA: DMA CRC Data Register

      110
    • Register 9-6: DCRCXOR: DMA CRCXOR Enable Register

      110
    • Register 9-7: DCHxCON: DMA Channel ‘x’ Control Register

      111
    • Register 9-8: DCHxECON: DMA Channel ‘x’ Event Control Register

      112
    • Register 9-9: DCHxINT: DMA Channel ‘x’ Interrupt Control Register (Continued)

      113
    • Register 9-10: DCHxSSA: DMA Channel ‘x’ Source Start Address Register

      115
    • Register 9-11: DCHxDSA: DMA Channel ‘x’ Destination Start Address Register

      115
    • Register 9-12: DCHxSSIZ: DMA Channel ‘x’ Source Size Register

      116
    • Register 9-13: DCHxDSIZ: DMA Channel ‘x’ Destination Size Register

      116
    • Register 9-14: DCHxSPTR: DMA Channel ‘x’ Source Pointer Register

      117
    • Register 9-15: DCHxDPTR: DMA Channel ‘x’ Destination Pointer Register

      117
    • Register 9-16: DCHxCSIZ: DMA Channel ‘x’ Cell-Size Register

      118
    • Register 9-17: DCHxCPTR: DMA Channel ‘x’ Cell Pointer Register

      118
    • Register 9-18: DCHxDAT: DMA Channel ‘x’ Pattern Data Register

      119
  • 10.0 USB On-The-Go (OTG)

    121
    • FIGURE 10-1: PIC32MX1XX/2XX Family USB Interface Diagram

      122
    • Register 10-1: U1OTGIR: USB OTG Interrupt Status Register

      123
    • Register 10-2: U1OTGIE: USB OTG Interrupt Enable Register

      124
    • Register 10-3: U1OTGSTAT: USB OTG Status Register

      125
    • Register 10-4: U1OTGCON: USB OTG Control Register

      126
    • Register 10-5: U1PWRC: USB Power Control Register

      127
    • Register 10-6: U1IR: USB Interrupt Register

      128
    • Register 10-7: U1IE: USB Interrupt Enable Register

      129
    • Register 10-8: U1EIR: USB Error Interrupt Status Register

      130
    • Register 10-9: U1EIE: USB Error Interrupt Enable Register

      132
    • Register 10-10: U1STAT: USB Status Register

      133
    • Register 10-11: U1CON: USB Control Register

      134
    • Register 10-12: U1ADDR: USB Address Register

      136
    • Register 10-13: U1FRML: USB Frame Number Low Register

      136
    • Register 10-14: U1FRMH: USB Frame Number High Register

      137
    • Register 10-15: U1TOK: USB Token Register

      137
    • Register 10-16: U1SOF: USB SOF Threshold Register

      138
    • Register 10-17: U1BDTP1: USB Buffer Descriptor Table Page 1 Register

      138
    • Register 10-18: U1BDTP2: USB Buffer Descriptor Table PAGE 2 Register

      139
    • Register 10-19: U1BDTP3: USB Buffer Descriptor Table PAGE 3 Register

      139
    • Register 10-20: U1CNFG1: USB Configuration 1 Register

      140
    • Register 10-21: U1EP0-U1EP15: USB Endpoint Control Register

      141
  • 11.0 I/O Ports

    143
    • FIGURE 11-1: Block Diagram of a Typical Multiplexed Port Structure

      143
    • 11.1 Parallel I/O (PIO) Ports

      144
    • 11.2 CLR, SET and INV Registers

      144
    • 11.3 Peripheral Pin Select

      145
      • FIGURE 11-2: Remappable Input Example for U1RX

        145
      • Table 11-1: Input Pin Selection

        146
      • FIGURE 11-3: Example of Multiplexing of Remappable Output for RPA0

        147
      • Table 11-2: Output Pin Selection

        148
      • Register 11-1: [pin name]R: Peripheral Pin Select Input Register

        149
      • Register 11-2: RPnR: Peripheral Pin Select Output Register

        149
      • Register 11-3: CNCONx: Change Notice control for PORTx Register (x = A, B, C)

        150
  • 12.0 Timer1

    151
    • 12.1 Additional Supported Features

      151
      • FIGURE 12-1: Timer1 Block Diagram

        151
      • Register 12-1: T1CON: Type A Timer Control Register (Continued)

        152
  • 13.0 Timer2/3, Timer4/5

    155
    • 13.1 Additional Supported Features

      155
      • FIGURE 13-1: Timer2-Timer5 Block Diagram (16-bit)

        155
      • FIGURE 13-2: Timer2/3, Timer4/5 Block Diagram (32-bit)

        156
      • Register 13-1: TxCON: Type B Timer Control Register

        157
  • 14.0 Input Capture

    159
    • FIGURE 14-1: Input Capture Block Diagram

      159
    • Register 14-1: ICxCON: Input Capture ‘x’ Control Register

      160
  • 15.0 Output Compare

    163
    • FIGURE 15-1: Output Compare Module Block Diagram

      163
    • Register 15-1: OCxCON: Output Compare ‘x’ Control Register

      164
  • 16.0 Serial Peripheral Interface (SPI)

    165
    • FIGURE 16-1: SPI Module Block Diagram

      165
    • Register 16-1: SPIx CON: SPI Control Register (Continued)

      166
    • Register 16-2: SPIxCON2: SPI Control Register 2

      169
    • Register 16-3: SPIxSTAT: SPI Status Register

      170
  • 17.0 Inter-Integrated Circuit™ (I2C™)

    173
    • FIGURE 17-1: I2C™ Block Diagram

      174
    • Register 17-1: I2CxCON: I2C™ Control Register (Continued)

      175
    • Register 17-2: I2CxSTAT: I2C™ Status Register

      177
  • 18.0 Universal Asynchronous Receiver Transmitter (UART)

    179
    • FIGURE 18-1: UART Simplified Block Diagram

      179
    • Register 18-1: UxMODE: UARTx Mode Register (Continued)

      180
    • Register 18-2: UxSTA: UARTx Status and Control Register

      182
    • FIGURE 18-2: UART Reception

      184
    • FIGURE 18-3: Transmission (8-bit or 9-bit Data)

      184
  • 19.0 Parallel Master Port (PMP)

    185
    • FIGURE 19-1: PMP Module Pinout and Connections to External Devices

      185
    • Register 19-1: PMCON: Parallel Port Control Register

      186
    • Register 19-2: PMMODE: Parallel Port Mode Register

      188
    • Register 19-3: PMADDR: Parallel Port Address Register

      190
    • Register 19-4: PMAEN: Parallel Port Pin Enable Register

      191
    • Register 19-5: PMSTAT: Parallel Port Status Register (Slave modes only)

      192
  • 20.0 Real-Time Clock and Calendar (RTCC)

    193
    • FIGURE 20-1: RTCC Block Diagram

      193
    • Register 20-1: RTCCON: RTC Control Register

      194
    • Register 20-2: RTCALRM: RTC ALARM Control Register (Continued)

      196
    • Register 20-3: RTCTIME: RTC Time Value Register

      198
    • Register 20-4: RTCDATE: RTC Date Value Register

      199
    • Register 20-5: ALRMTIME: Alarm Time Value Register

      200
    • Register 20-6: ALRMDATE: Alarm Date Value Register

      201
  • 21.0 10-bit Analog-to-Digital Converter (ADC)

    203
    • FIGURE 21-1: ADC1 Module Block Diagram

      203
    • FIGURE 21-2: ADC Conversion Clock Period Block Diagram

      204
    • Register 21-1: AD1CON1: ADC Control Register 1

      205
    • Register 21-2: AD1CON2: ADC Control Register 2

      207
    • Register 21-3: AD1CON3: ADC Control Register 3

      208
    • Register 21-4: AD1CHS: ADC Input Select Register

      209
    • Register 21-5: AD1CSSL: ADC Input Scan Select Register

      210
  • 22.0 Comparator

    211
    • FIGURE 22-1: Comparator Block Diagram

      211
    • Register 22-1: CMxCON: Comparator Control Register

      212
    • Register 22-2: CMSTAT: Comparator Status Register

      213
  • 23.0 Comparator Voltage Reference (CVref)

    215
    • FIGURE 23-1: Comparator Voltage Reference Block Diagram

      215
    • Register 23-1: CVRCON: Comparator Voltage Reference Control Register

      216
  • 24.0 Charge Time Measurement Unit (CTMU)

    217
    • FIGURE 24-1: CTMU Block Diagram

      217
    • Register 24-1: CTMUCON: CTMU Control Register

      218
  • 25.0 Power-Saving Features

    221
    • 25.1 Power Saving with CPU Running

      221
    • 25.2 CPU Halted Methods

      221
    • 25.3 Power-Saving Operation

      221
    • 25.4 Peripheral Module Disable

      223
      • Table 25-1: Peripheral Module Disable Bits and Locations

        223
  • 26.0 Special Features

    225
    • 26.1 Configuration Bits

      225
      • Register 26-1: DEVCFG0: Device Configuration Word 0

        226
      • Register 26-2: DEVCFG1: Device Configuration Word 1 (Continued)

        228
      • Register 26-3: DEVCFG2: Device Configuration Word 2 (Continued)

        230
      • Register 26-4: DEVCFG3: Device Configuration Word 3

        232
      • Register 26-5: CFGCON: Configuration Control Register

        233
      • Register 26-6: DEVID: Device and Revision ID Register

        234
    • 26.2 Watchdog Timer (WDT)

      235
      • Figure 26-1: Watchdog TIMER and Power-Up Timer Block Diagram

        235
      • Register 26-7: WDTCON: Watchdog Timer Control Register

        236
    • 26.3 On-Chip Voltage Regulator

      237
      • Figure 26-2: Connections for the On-Chip Regulator

        237
    • 26.4 Programming and Diagnostics

      237
      • Figure 26-3: Block Diagram of Programming, Debugging and Trace Ports

        237
  • 27.0 Instruction Set

    239
  • 28.0 Development Support

    241
    • 28.1 MPLAB X Integrated Development Environment Software

      241
    • 28.2 MPLAB XC Compilers

      242
    • 28.3 MPASM Assembler

      242
    • 28.4 MPLINK Object Linker/ MPLIB Object Librarian

      242
    • 28.5 MPLAB Assembler, Linker and Librarian for Various Device Families

      242
    • 28.6 MPLAB X SIM Software Simulator

      243
    • 28.7 MPLAB REAL ICE In-Circuit Emulator System

      243
    • 28.8 MPLAB ICD 3 In-Circuit Debugger System

      243
    • 28.9 PICkit 3 In-Circuit Debugger/ Programmer

      243
    • 28.10 MPLAB PM3 Device Programmer

      243
    • 28.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

      244
    • 28.12 Third-Party Development Tools

      244
  • 29.0 Electrical Characteristics

    245
    • 29.1 DC Characteristics

      246
      • Table 29-1: Operating MIPS vs. Voltage

        246
      • Table 29-2: Thermal Operating Conditions

        246
      • Table 29-3: Thermal Packaging Characteristics

        246
      • Table 29-4: DC Temperature and Voltage Specifications

        247
      • Table 29-5: DC Characteristics: Operating Current (Idd)

        248
      • Table 29-6: DC Characteristics: Idle Current (Iidle)

        249
      • Table 29-7: DC Characteristics: Power-Down Current (Ipd)

        250
      • Table 29-8: DC Characteristics: I/O Pin Input Specifications

        251
      • TABLE 29-9: DC Characteristics: I/O Pin Output Specifications

        252
      • Table 29-10: Electrical Characteristics: BOR

        252
      • Table 29-11: DC Characteristics: Program Memory

        253
      • Table 29-12: Comparator Specifications

        254
      • Table 29-13: Internal Voltage Regulator Specifications

        254
    • 29.2 AC Characteristics and Timing Parameters

      255
      • Figure 29-1: Load Conditions for Device Timing Specifications

        255
      • Table 29-14: Capacitive Loading Requirements on Output Pins

        255
      • Figure 29-2: External Clock Timing

        255
      • Table 29-15: External Clock Timing Requirements

        256
      • Table 29-16: PLL Clock Timing Specifications

        257
      • Table 29-17: Internal FRC Accuracy

        257
      • Table 29-18: Internal LPRC Accuracy

        257
      • Figure 29-3: I/O Timing Characteristics

        258
      • Table 29-19: I/O Timing Requirements

        258
      • Figure 29-4: Power-On Reset Timing Characteristics

        259
      • Figure 29-5: External Reset Timing Characteristics

        260
      • Table 29-20: Resets Timing

        260
      • Figure 29-6: Timer1, 2, 3, 4, 5 External Clock Timing Characteristics

        261
      • Table 29-21: Timer1 External Clock Timing Requirements

        261
      • Table 29-22: Timer2, 3, 4, 5 External Clock Timing Requirements

        262
      • Figure 29-7: Input Capture (CAPx) Timing Characteristics

        262
      • Table 29-23: Input Capture Module Timing Requirements

        262
      • Figure 29-8: Output Compare Module (OCx) Timing Characteristics

        263
      • Table 29-24: Output Compare Module Timing Requirements

        263
      • Figure 29-9: OCx/PWM Module Timing Characteristics

        263
      • Table 29-25: Simple OCx/PWM Mode Timing Requirements

        263
      • Figure 29-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics

        264
      • Table 29-26: SPIx Master Mode (CKE = 0) Timing Requirements

        264
      • Figure 29-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics

        265
      • Table 29-27: SPIx Module Master Mode (CKE = 1) Timing Requirements

        265
      • Figure 29-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics

        266
      • Table 29-28: SPIx Module Slave Mode (CKE = 0) Timing Requirements

        266
      • Figure 29-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics

        267
      • Table 29-29: SPIx Module Slave Mode (CKE = 1) Timing Requirements

        267
      • Figure 29-14: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

        269
      • Figure 29-15: I2Cx Bus Data Timing Characteristics (Master Mode)

        269
      • Table 29-30: I2Cx Bus Data Timing Requirements (Master Mode)

        270
      • Figure 29-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)

        272
      • Figure 29-17: I2Cx Bus Data Timing Characteristics (Slave Mode)

        272
      • Table 29-31: I2Cx Bus Data Timing Requirements (Slave Mode)

        273
      • Table 29-32: ADC Module Specifications

        275
      • Table 29-33: 10-bit Conversion Rate Parameters

        277
      • Table 29-34: Analog-to-Digital Conversion Timing Requirements

        278
      • Figure 29-18: Analog-to-Digital Conversion (10-bit Mode) Timing Characteristics (ASAM = 0, SSRC<2:0> = 000)

        279
      • Figure 29-19: Analog-to-Digital Conversion (10-bit mode) Timing Characteristics (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

        280
      • Figure 29-20: Parallel Slave Port Timing

        281
      • Table 29-35: Parallel Slave Port Requirements

        282
      • Figure 29-21: Parallel Master Port Read Timing Diagram

        282
      • Table 29-36: Parallel Master Port Read Timing Requirements

        283
      • Figure 29-22: Parallel Master Port Write Timing Diagram

        283
      • Table 29-37: Parallel Master Port Write Timing Requirements

        284
      • Table 29-38: OTG Electrical Specifications

        284
      • TABLE 29-39: CTMU Current Source Specifications

        285
      • Figure 29-23: EJTAG Timing Characteristics

        286
      • Table 29-40: EJTAG Timing Requirements

        286
  • 30.0 50 MHz Electrical Characteristics

    287
    • 30.1 DC Characteristics

      288
      • Table 30-1: Operating MIPS vs. Voltage

        288
      • Table 30-2: DC Characteristics: Operating Current (Idd)

        288
      • Table 30-3: DC Characteristics: Idle Current (Iidle)

        289
      • Table 30-4: DC Characteristics: Power-Down Current (Ipd)

        289
      • Table 30-5: External Clock Timing Requirements

        290
      • Table 30-6: SPIx Master Mode (CKE = 0) Timing Requirements

        290
      • Table 30-7: SPIx Module Master Mode (CKE = 1) Timing Requirements

        290
      • Table 30-8: SPIx Module Slave Mode (CKE = 0) Timing Requirements

        291
      • Table 30-9: SPIx Module Slave Mode (CKE = 1) Timing Requirements

        291
  • 31.0 DC and AC Device Characteristics Graphs

    293
    • FIGURE 31-1: I/O Output Voltage High (Voh)

      293
    • FIGURE 31-2: I/O Output Voltage Low (Vol)

      293
    • FIGURE 31-3: Typical Ipd Current @ Vdd = 3.3V

      294
    • FIGURE 31-4: Typical Idd Current @ Vdd = 3.3V

      294
    • FIGURE 31-5: Typical Iidle Current @ Vdd = 3.3V

      294
    • FIGURE 31-6: Typical FRC Frequency @ Vdd = 3.3V

      295
    • FIGURE 31-7: Typical LPRC Frequency @ Vdd = 3.3V

      295
    • FIGURE 31-8: Typical CTMU Temperature DIODE Forward Voltage

      295
  • 32.0 Packaging Information

    297
    • 32.1 Package Marking Information

      297
    • 32.1 Package Marking Information (Continued)

      298
    • 32.2 Package Details

      299
  • Appendix A: Revision History

    315
    • TABLE A-1: Major Section Updates

      315
    • TABLE A-2: Major Section Updates

      317
    • TABLE A-3: Major Section Updates

      318
    • TABLE A-4: Major Section Updates

      319
    • TABLE A-5: Major Section Updates (Continued)

      320
  • INDEX

    323
  • The Microchip Web Site

    327
  • Customer Change Notification Service

    327
  • Customer Support

    327
  • Product Identification System

    328
• Worldwide Sales and Service

  330