Microchip Technology TDGL019 Data Sheet
© 2011-2014 Microchip Technology Inc.
DS60001168F-page 141
PIC32MX1XX/2XX
REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
7:0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LSPD
RETRYDIS
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
bit 7
LSPD:
Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1
= Direct connection to a Low-Speed device enabled
0
= Direct connection to a Low-Speed device disabled; hub required with PRE_PID
bit 6
RETRYDIS:
Retry Disable bit (Host mode and U1EP0 only)
1
= Retry NAKed transactions disabled
0
= Retry NAKed transactions enabled; retry done in hardware
bit 5
Unimplemented:
Read as ‘0’
bit 4
EPCONDIS:
Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN = 1:
1
= Disable Endpoint n from Control transfers; only TX and RX transfers allowed
0
= Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
Otherwise, this bit is ignored.
bit 3
EPRXEN:
Endpoint Receive Enable bit
1
= Endpoint n receive is enabled
0
= Endpoint n receive is disabled
bit 2
EPTXEN:
Endpoint Transmit Enable bit
1
= Endpoint n transmit is enabled
0
= Endpoint n transmit is disabled
bit 1
EPSTALL:
Endpoint Stall Status bit
1
= Endpoint n was stalled
0
= Endpoint n was not stalled
bit 0
EPHSHK:
Endpoint Handshake Enable bit
1
= Endpoint Handshake is enabled
0
= Endpoint Handshake is disabled (typically used for isochronous endpoints)