Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 152
© 2011-2014 Microchip Technology Inc.
REGISTER 12-1:
T1CON: TYPE A TIMER CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R/W-0
U-0
R/W-0
R/W-0
R-0
U-0
U-0
U-0
ON
(1)
—
SIDL
TWDIS
TWIP
—
—
—
7:0
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
TGATE
—
TCKPS<1:0>
—
TSYNC
TCS
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 15
ON:
Timer On bit
(1)
1
= Timer is enabled
0
= Timer is disabled
bit 14
Unimplemented:
Read as ‘0’
bit 13
SIDL:
Stop in Idle Mode bit
1
= Discontinue module operation when the device enters Idle mode
0
= Continue module operation when the device enters Idle mode
bit 12
TWDIS:
Asynchronous Timer Write Disable bit
1
= Writes to Timer1 are ignored until pending write operation completes
0
= Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11
TWIP:
Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1
1
= Asynchronous write to the Timer1 register in progress
0
= Asynchronous write to Timer1 register is complete
In Synchronous Timer mode:
This bit is read as ‘0’.
This bit is read as ‘0’.
bit 10-8
Unimplemented:
Read as ‘0’
bit 7
TGATE:
Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1
This bit is ignored.
When TCS = 0:
1
= Gated time accumulation is enabled
0
= Gated time accumulation is disabled
bit 6
Unimplemented:
Read as ‘0’
bit 5-4
TCKPS<1:0>:
Timer Input Clock Prescale Select bits
11
= 1:256 prescale value
10
= 1:64 prescale value
01
= 1:8 prescale value
00
= 1:1 prescale value
Note 1:
When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.