Microchip Technology TDGL019 Data Sheet
© 2011-2014 Microchip Technology Inc.
DS60001168F-page 157
PIC32MX1XX/2XX
REGISTER 13-1:
TXCON: TYPE B TIMER CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
(1,3)
—
SIDL
(4)
—
—
—
—
—
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
TGATE
(3)
TCKPS<2:0>
(3)
T32
(2)
—
TCS
(3)
—
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
Unimplemented:
Read as ‘0’
bit 15
ON:
Timer On bit
(1,3)
1
= Module is enabled
0
= Module is disabled
bit 14
Unimplemented:
Read as ‘0’
bit 13
SIDL:
Stop in Idle Mode bit
(4)
1
= Discontinue module operation when the device enters Idle mode
0
= Continue module operation when the device enters Idle mode
bit 12-8
Unimplemented:
Read as ‘0’
bit 7
TGATE:
Timer Gated Time Accumulation Enable bit
(3)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1
This bit is ignored and is read as ‘0’.
When TCS = 0:
1
= Gated time accumulation is enabled
0
= Gated time accumulation is disabled
bit 6-4
TCKPS<2:0>:
Timer Input Clock Prescale Select bits
(3)
111
= 1:256 prescale value
110
= 1:64 prescale value
101
= 1:32 prescale value
100
= 1:16 prescale value
011
= 1:8 prescale value
010
= 1:4 prescale value
001
= 1:2 prescale value
000
= 1:1 prescale value
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2:
This bit is available only on even numbered timers (Timer2 and Timer4).
3:
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3, and Timer5). All
timer functions are set through the even numbered timers.
timer functions are set through the even numbered timers.
4:
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
in Idle mode.