Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 170
© 2011-2014 Microchip Technology Inc.
REGISTER 16-3:
SPIxSTAT: SPI STATUS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
RXBUFELM<4:0>
23:16
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
TXBUFELM<4:0>
15:8
U-0
U-0
U-0
R/C-0, HS
R-0
U-0
U-0
R-0
—
—
—
FRMERR
SPIBUSY
—
—
SPITUR
7:0
R-0
R/W-0
R-0
U-0
R-1
U-0
R-0
R-0
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF
Legend:
C = Clearable bit
HS = Set in hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
FRMERR:
SPI Frame Error status bit
1
= Frame error detected
0
= No Frame error detected
This bit is only valid when FRMEN = 1.
bit 11
SPIBUSY:
SPI Activity Status bit
1
= SPI peripheral is currently busy with some transactions
0
= SPI peripheral is currently idle
bit 10-9
Unimplemented:
Read as ‘0’
bit 8
SPITUR:
Transmit Under Run bit
1
= Transmit buffer has encountered an underrun condition
0
= Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling (ON bit = 0)
and re-enabling (ON bit = 1) the module, or writing a ‘0’ to SPITUR.
and re-enabling (ON bit = 1) the module, or writing a ‘0’ to SPITUR.
bit 7
SRMT:
Shift Register Empty bit (valid only when ENHBUF = 1)
1
= When SPI module shift register is empty
0
= When SPI module shift register is not empty
bit 6
SPIROV:
Receive Overflow Flag bit
1
= A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0
= No overflow has occurred
This bit is set in hardware; can bit only be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the
module, or by writing a ‘0’ to SPIROV.
module, or by writing a ‘0’ to SPIROV.
bit 5
SPIRBE:
RX FIFO Empty bit (valid only when ENHBUF = 1)
1
= RX FIFO is empty (CRPTR = SWPTR)
0
= RX FIFO is not empty (CRPTR
≠
SWPTR)
bit 4
Unimplemented:
Read as ‘0’