Microchip Technology TDGL019 Data Sheet
© 2011-2014 Microchip Technology Inc.
DS60001168F-page 177
PIC32MX1XX/2XX
REGISTER 17-2:
I2C
X
STAT: I
2
C™ STATUS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R-0, HSC
R-0, HSC
U-0
U-0
U-0
R/C-0, HS
R-0, HSC
R-0, HSC
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
7:0
R/C-0, HS
R/C-0, HS
R-0, HSC
R/C-0, HSC
R/C-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
Legend:
HS = Set in hardware
HSC = Hardware set/cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 15
ACKSTAT:
Acknowledge Status bit (when operating as I
2
C master, applicable to master transmit operation)
1
= Acknowledge was not received from slave
0
= Acknowledge was received from slave
Hardware set or clear at end of slave Acknowledge.
bit 14
TRSTAT:
Transmit Status bit (when operating as I
2
C master, applicable to master transmit operation)
1
= Master transmit is in progress (8 bits + ACK)
0
= Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10
bit 10
BCL:
Master Bus Collision Detect bit
1
= A bus collision has been detected during a master operation
0
= No collision
Hardware set at detection of bus collision. This condition can only be cleared by disabling (ON bit = 0) and
re-enabling (ON bit = 1) the module.
re-enabling (ON bit = 1) the module.
bit 9
GCSTAT:
General Call Status bit
1
= General call address was received
0
= General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
bit 8
ADD10:
10-bit Address Status bit
1
= 10-bit address was matched
0
= 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7
IWCOL:
Write Collision Detect bit
1
= An attempt to write the I2CxTRN register failed because the I
2
C module is busy
0
= No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV:
Receive Overflow Flag bit
1
= A byte was received while the I2CxRCV register is still holding the previous byte
0
= No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5
D_A:
Data/Address bit (when operating as I
2
C slave)
1
= Indicates that the last byte received was data
0
= Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.