Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 180
© 2011-2014 Microchip Technology Inc.
REGISTER 18-1:
UxMODE: UARTx MODE REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
ON
(1)
—
SIDL
IREN
RTSMD
—
UEN<1:0>
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 15
ON:
UARTx Enable bit
(1)
1
= UARTx is enabled. UARTx pins are controlled by UARTx as defined by the UEN<1:0> and UTXEN
control bits.
0
= UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
registers; UARTx power consumption is minimal.
bit 14
Unimplemented:
Read as ‘0’
bit 13
SIDL:
Stop in Idle Mode bit
1
= Discontinue module operation when the device enters Idle mode
0
= Continue module operation when the device enters Idle mode
bit 12
IREN:
IrDA Encoder and Decoder Enable bit
1
= IrDA is enabled
0
= IrDA is disabled
bit 11
RTSMD:
Mode Selection for UxRTS Pin bit
1
= UxRTS pin is in Simplex mode
0
= UxRTS pin is in Flow Control mode
bit 10
Unimplemented:
Read as ‘0’
bit 9-8
UEN<1:0>:
UARTx Enable bits
11
= UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10
= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01
= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00
= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7
WAKE:
Enable Wake-up on Start bit Detect During Sleep Mode bit
1
= Wake-up enabled
0
= Wake-up disabled
bit 6
LPBACK:
UARTx Loopback Mode Select bit
1
= Loopback mode is enabled
0
= Loopback mode is disabled
Note 1:
When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.