Microchip Technology TDGL019 Data Sheet
© 2011-2014 Microchip Technology Inc.
DS60001168F-page 191
PIC32MX1XX/2XX
REGISTER 19-4:
PMAEN: PARALLEL PORT PIN ENABLE REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
PTEN14
—
—
—
PTEN<10:8>
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN<7:0>
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 15-14 PTEN14: PMCS1 Address Port Enable bits
bit 15-14 PTEN14: PMCS1 Address Port Enable bits
1
= PMA14 functions as either PMA14 or PMCS1
(1)
0
= PMA14 functions as port I/O
bit 13-11 Unimplemented: Read as ‘0’
bit 10-2
bit 10-2
PTEN<10:2>:
PMP Address Port Enable bits
1
= PMA<10:2> function as PMP address lines
0
= PMA<10:2> function as port I/O
bit 1-0
PTEN<1:0>:
PMALH/PMALL Address Port Enable bits
1
= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
(2)
0
= PMA1 and PMA0 pads functions as port I/O
Note 1:
The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register.
2:
The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by bits ADRMUX<1:0> in the PMCON register.
selected by bits ADRMUX<1:0> in the PMCON register.