Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 194
© 2011-2014 Microchip Technology Inc.
REGISTER 20-1:
RTCCON: RTC CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
CAL<9:8>
23:16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL<7:0>
15:8
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ON
(1,2)
—
SIDL
—
—
—
—
—
7:0
R/W-0
R-0
U-0
U-0
R/W-0
R-0
R-0
R/W-0
RTSECSEL
(3)
RTCCLKON
—
—
RTCWREN
(4)
RTCSYNC HALFSEC
(5)
RTCOE
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value
bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value
0111111111
= Maximum positive adjustment, adds 511 RTC clock pulses every one minute
•
•
•
•
•
0000000001
= Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000
= No adjustment
1111111111
= Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
•
•
•
•
•
1000000000
= Minimum negative adjustment, subtracts 512 clock pulses every one minute
bit 15
ON:
RTCC On bit
(1,2)
1
= RTCC module is enabled
0
= RTCC module is disabled
bit 14
Unimplemented:
Read as ‘0’
bit 13
SIDL:
Stop in Idle Mode bit
1
= Disables the PBCLK to the RTCC when the device enters Idle mode
0
= Continue normal operation when the device enters Idle mode
bit 12-8
Unimplemented:
Read as ‘0’
bit 7
RTSECSEL:
RTCC Seconds Clock Output Select bit
(3)
1
= RTCC Seconds Clock is selected for the RTCC pin
0
= RTCC Alarm Pulse is selected for the RTCC pin
bit 6
RTCCLKON:
RTCC Clock Enable Status bit
1
= RTCC Clock is actively running
0
= RTCC Clock is not running
Note 1:
The ON bit is only writable when RTCWREN = 1.
2:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
3:
Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
4:
The RTCWREN bit can be set only when the write sequence is enabled.
5:
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note:
This register is reset only on a Power-on Reset (POR).