Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 212
© 2011-2014 Microchip Technology Inc.
REGISTER 22-1:
CMXCON: COMPARATOR CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R-0
ON
(1)
COE
CPOL
(2)
—
—
—
—
COUT
7:0
R/W-1
R/W-1
U-0
R/W-0
U-0
U-0
R/W-1
R/W-1
EVPOL<1:0>
—
CREF
—
—
CCH<1:0>
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 15
ON:
Comparator ON bit
(1)
1
= Module is enabled. Setting this bit does not affect the other bits in this register
0
= Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this
register
bit 14
COE:
Comparator Output Enable bit
1
= Comparator output is driven on the output CxOUT pin
0
= Comparator output is not driven on the output CxOUT pin
bit 13
CPOL:
Comparator Output Inversion bit
(2)
1
= Output is inverted
0
= Output is not inverted
bit 12-9
Unimplemented:
Read as ‘0’
bit 8
COUT:
Comparator Output bit
1
= Output of the Comparator is a ‘1’
0
= Output of the Comparator is a ‘0’
bit 7-6
EVPOL<1:0>:
Interrupt Event Polarity Select bits
11
= Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10
= Comparator interrupt is generated on a high-to-low transition of the comparator output
01
= Comparator interrupt is generated on a low-to-high transition of the comparator output
00
= Comparator interrupt generation is disabled
bit 5
Unimplemented:
Read as ‘0’
bit 4
CREF:
Comparator Positive Input Configure bit
1
= Comparator non-inverting input is connected to the internal CV
REF
0
= Comparator non-inverting input is connected to the C
X
INA pin
bit 3-2
Unimplemented:
Read as ‘0’
bit 1-0
CCH<1:0>:
Comparator Negative Input Select bits for Comparator
11
= Comparator inverting input is connected to the IV
REF
10
= Comparator inverting input is connected to the CxIND pin
01
= Comparator inverting input is connected to the CxINC pin
00
= Comparator inverting input is connected to the CxINB pin
Note 1:
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2:
Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.
interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.