Microchip Technology TDGL019 Data Sheet

DS60001168F-page 266

© 2011-2014 Microchip Technology Inc.

SS

X

SCK

X

(CKP = 0)

SCK

X

(CKP = 1)

SDO

X

SP50

SP40

SP41

SP30,SP31

SP51

SP35

MSb

LSb

Bit 14 - - - - - -1

Bit 14 - - - -1

LSb In

SP52

SP73

SP72

SP72

SP73

SP71

SP70

Refer to 

 for load conditions.

SDI

X

MSb In

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C 

≤ T

A

 

≤ +85°C for Industrial

-40°C 

≤ T

A

 

≤ +105°C for V-temp

SP70

T

SC

L

SCKx Input Low Time (Note 3)

T

SCK

/2

—

—

ns

—

SP71

T

SC

H

SCKx Input High Time (Note 3)

T

SCK

/2

—

—

ns

—

SP72

T

SC

F

SCKx Input Fall Time

—

—

—

ns

See parameter DO32

SP73

T

SC

R

SCKx Input Rise Time

—

—

—

ns

See parameter DO31

SP30

T

DO

F

SDOx Data Output Fall Time (Note 4)

—

—

—

ns

See parameter DO32

SP31

T

DO

R

SDOx Data Output Rise Time (Note 4)

—

—

—

ns

See parameter DO31

SP35

T

SC

H2

DO

V,

T

SC

L2

DO

V

SDOx Data Output Valid after
SCKx Edge

—

—

15

ns

V

DD

 > 2.7V

—

—

20

ns

V

DD

 < 2.7V

SP40

T

DI

V2

SC

H, 

T

DI

V2

SC

L

Setup Time of SDIx Data Input
to SCKx Edge

10

—

—

ns

—

SP41

T

SC

H2

DI

L, 

T

SC

L2

DI

L

Hold Time of SDIx Data Input
to SCKx Edge 

10

—

—

ns

—

SP50

T

SS

L2

SC

H, 

T

SS

L2

SC

L

SSx 

↓ to SCKx ↑ or SCKx Input

175

—

—

ns

—

SP51

T

SS

H2

DO

Z SSx 

↑ to SDOx Output 

High-Impedance (Note 3)

5

—

25

ns

—

SP52

T

SC

H2

SS

H

T

SC

L2

SS

H

SSx after SCKx Edge

T

SCK

 + 20

—

—

ns

—

These parameters are characterized, but not tested in manufacturing.

Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only 
and are not tested.

The minimum clock period for SCKx is 50 ns.

Assumes 50 pF load on all SPIx pins.