Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 34
© 2011-2014 Microchip Technology Inc.
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors.
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors.
lists
the exception types in order of priority.
TABLE 3-3:
MIPS32
®
M4K
®
PROCESSOR CORE EXCEPTION TYPES
3.3
Power Management
The MIPS M4K processor core offers many power man-
agement features, including low-power design, active
power management and power-down modes of opera-
tion. The core is a static design that supports slowing or
Halting the clocks, which reduces system power con-
sumption during Idle periods.
agement features, including low-power design, active
power management and power-down modes of opera-
tion. The core is a static design that supports slowing or
Halting the clocks, which reduces system power con-
sumption during Idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see
through execution of the WAIT instruction. For more
information on power management, see
3.4
EJTAG Debug Support
The MIPS M4K processor core provides an Enhanced
JTAG (EJTAG) interface for use in the software debug
of application and kernel code. In addition to standard
User mode and Kernel modes of operation, the M4K
core provides a Debug mode that is entered after a
debug exception (derived from a hardware breakpoint,
single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans-
ferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.
JTAG (EJTAG) interface for use in the software debug
of application and kernel code. In addition to standard
User mode and Kernel modes of operation, the M4K
core provides a Debug mode that is entered after a
debug exception (derived from a hardware breakpoint,
single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans-
ferring test data in and out of the core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.
Exception
Description
Reset
Assertion MCLR or a Power-on Reset (POR).
DSS
EJTAG debug single step.
DINT
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
EjtagBrk bit in the ECR register.
NMI
Assertion of NMI signal.
Interrupt
Assertion of unmasked hardware or software interrupt signal.
DIB
EJTAG debug hardware instruction break matched.
AdEL
Fetch address alignment error.
Fetch reference to protected address.
Fetch reference to protected address.
IBE
Instruction fetch bus error.
DBp
EJTAG breakpoint (execution of SDBBP instruction).
Sys
Execution of SYSCALL instruction.
Bp
Execution of BREAK instruction.
RI
Execution of a reserved instruction.
CpU
Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU
Execution of a CorExtend instruction when CorExtend is not enabled.
Ov
Execution of an arithmetic instruction that overflowed.
Tr
Execution of a trap (when trap condition is true).
DDBL/DDBS
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
AdEL
Load address alignment error.
Load reference to protected address.
Load reference to protected address.
AdES
Store address alignment error.
Store to protected address.
Store to protected address.
DBE
Load or store bus error.
DDBL
EJTAG data hardware breakpoint matched in load data compare.