Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 80
© 2011-2014 Microchip Technology Inc.
REGISTER 5-1:
NVMCON: PROGRAMMING CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R/W-0
R/W-0
R-0
R-0
R-0
U-0
U-0
U-0
WR
WREN
WRERR
(1)
LVDERR
(1)
LVDSTAT
(1)
—
—
—
7:0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
NVMOP<3:0>
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 15
WR:
Write Control bit
This bit is writable when WREN = 1 and the unlock sequence is followed.
1
= Initiate a Flash operation. Hardware clears this bit when the operation completes
0
= Flash operation is complete or inactive
bit 14
WREN:
Write Enable bit
This is the only bit in this register reset by a device Reset.
1
= Enable writes to WR bit and enables LVD circuit
0
= Disable writes to WR bit and disables LVD circuit
bit 13
WRERR:
Write Error bit
(1)
This bit is read-only and is automatically set by hardware.
1
= Program or erase sequence did not complete successfully
0
= Program or erase sequence completed normally
bit 12
LVDERR:
Low-Voltage Detect Error bit (LVD circuit must be enabled)
(1)
This bit is read-only and is automatically set by hardware.
1
= Low-voltage detected (possible data corruption, if WRERR is set)
0
= Voltage level is acceptable for programming
bit 11
LVDSTAT:
Low-Voltage Detect Status bit (LVD circuit must be enabled)
(1)
This bit is read-only and is automatically set and cleared by the hardware.
1
= Low-voltage event is active
0
= Low-voltage event is not active
bit 10-4
Unimplemented:
Read as ‘0’
bit 3-0
NVMOP<3:0>:
NVM Operation bits
These bits are writable when WREN = 0.
1111
= Reserved
•
•
•
•
•
0111
= Reserved
0110
= No operation
0101
= Program Flash Memory (PFM) erase operation: erases PFM, if all pages are not write-protected
0100
= Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011
= Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010
= No operation
0001
= Word program operation: programs word selected by NVMADDR, if it is not write-protected
0000
= No operation
Note 1:
This bit is cleared by setting NVMOP == ‘b0000, and initiating a Flash operation (i.e., WR).