Microchip Technology MCP1631RD-MCC2 Data Sheet

 2006-2012 Microchip Technology Inc.

DS41291G-page 139

11.6.1

HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCPx/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see 

).

This mode can be used for Half-Bridge applications, as
shown in 

, or for Full-Bridge applications,

where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in Half-
Bridge power devices. The value of the PDC<6:0> bits of
the PWM1CON register sets the number of instruction
cycles before the output is driven active. If the value is
greater than the duty cycle, the corresponding output
remains inactive during the entire cycle. See

 for more details of the dead-band delay

operations.

Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.

Period

Pulse Width

td

td

P1A

P1B

td = Dead-Band Delay

Period

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

P1A

P1B

FET

Driver

FET

Driver

Load

+

-

+

-

FET

Driver

FET

Driver

V+

Load

FET

Driver

FET

Driver

P1A

P1B