Microchip Technology MCP1631RD-MCC2 Data Sheet
PIC16F882/883/884/886/887
DS41291G-page 178
2006-2012 Microchip Technology Inc.
FIGURE 12-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 12-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCTL
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
INTCON
GIE PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PIE1
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
PIR1
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
RCREG
EUSART Receive Data Register
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TXREG
EUSART Transmit Data Register
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master
Reception.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)