Microchip Technology MCP1631RD-MCC2 Data Sheet
2006-2012 Microchip Technology Inc.
DS41291G-page 197
PIC16F882/883/884/886/887
13.4.3
MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset, or when the MSSP module is disabled.
Control of the I
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset, or when the MSSP module is disabled.
Control of the I
2
C bus may be taken when the P bit is
set, or the bus is idle, with both the S and P bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start condition
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start condition
13.4.4
I
2
C™ MASTER MODE SUPPORT
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
1.
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
1.
Assert a Start condition on SDA and SCL.
2.
Assert a Repeated Start condition on SDA and
SCL.
SCL.
3.
Write to the SSPBUF register initiating
transmission of data/address.
transmission of data/address.
4.
Generate a Stop condition on SDA and SCL.
5.
Configure the I
2
C port to receive data.
6.
Generate an Acknowledge condition at the end
of a received byte of data.
of a received byte of data.
FIGURE 13-10:
MSSP BLOCK DIAGRAM (I
2
C™ MASTER MODE)
Note:
The MSSP module, when configured in I
2
C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
imitate transmission, before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
imitate transmission, before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Read
Write
SSPSR
Start bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb
LSb
SDA
Acknowledge
Generate
SCL
SCL In
Bus Collision
SDA In
Receiv
e E
nable
Cl
o
ck
C
n
tl
Clock Ar
bi
tr
at
e/
W
C
O
L
Det
e
ct
(hold of
f clock
s
ource)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM<3:0>
Note: I/O pins have diode protection to V
DD
and V
SS
.
Start bit Detect
Stop bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV