Microchip Technology MCP1631RD-MCC2 Data Sheet
PIC16F882/883/884/886/887
DS41291G-page 206
2006-2012 Microchip Technology Inc.
FIGURE 13-18:
STOP CONDITION RECEIVE OR TRANSMIT MODE
13.4.12
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (
receive, transmit or Repeated Start/Stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (
).
13.4.13
SLEEP OPERATION
While in Sleep mode, the I
2
C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
13.4.14
EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
current transfer.
FIGURE 13-19:
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2
Set PEN
Falling edge of
SCL = 1 for T
BRG
, followed by SDA = 1 for T
BRG
9th clock
SCL brought high after T
BRG
Note: T
BRG
= one Baud Rate Generator period.
T
BRG
T
BRG
after SDA sampled high, P bit (SSPSTAT) is set
T
BRG
to set up Stop condition
ACK
P
T
BRG
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
hardware and the SSPIF bit is set
SCL
SDA
BRG overflow,
Release SCL,
If SCL = 1, load BRG with
SSPADD<6:0>, and start count
BRG overflow occurs,
Release SCL, Slave device holds SCL low
Release SCL, Slave device holds SCL low
SCL = 1, BRG starts counting
clock high interval
SCL line sampled once every machine cycle (T
OSC
*4),
Hold off BRG until SCL is sampled high
T
BRG
T
BRG
T
BRG
to measure high time interval