Microchip Technology MCP1631RD-MCC2 Data Sheet
2006-2012 Microchip Technology Inc.
DS41291G-page 219
PIC16F882/883/884/886/887
14.2.5
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in
EC mode with PWRTE bit erased (PWRT disabled),
there will be no time-out at all. Figures
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in
EC mode with PWRTE bit erased (PWRT disabled),
there will be no time-out at all. Figures
and
depict time-out sequences. The device can
execute code from the INTOSC while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
enabling Two-Speed Start-up or Fail-Safe Monitor (see
and
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see
). This is useful for testing purposes or
to synchronize more than one
PIC16F882/883/884/886/887 device operating in par-
allel.
PIC16F882/883/884/886/887 device operating in par-
allel.
special registers, while
shows the Reset
conditions for all the registers.
14.2.6
POWER CONTROL (PCON)
REGISTER
REGISTER
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word
Register 1).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word
Register 1).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
DD
may have
gone too low).
For more information, see
For more information, see
TABLE 14-1:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 14-2:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
TABLE 14-3:
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Oscillator Configuration
Power-up
Brown-out Reset
Wake-up from
Sleep
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
T
PWRT
+
1024 • T
OSC
1024 • T
OSC
T
PWRT
+
1024 • T
OSC
1024 • T
OSC
1024 • T
OSC
LP, T1OSCIN = 1
T
PWRT
—
T
PWRT
—
—
RC, EC, INTOSC
T
PWRT
—
T
PWRT
—
—
POR
BOR
TO
PD
Condition
0
x
1
1
Power-on Reset
u
0
1
1
Brown-out Reset
u
u
0
u
WDT Reset
u
u
0
0
WDT Wake-up
u
u
u
u
MCLR Reset during normal operation
u
u
1
0
MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
PCON
—
—
ULPWUE SBOREN
—
—
POR
BOR
STATUS
IRP
RP1
RPO
TO
PD
Z
DC
C
Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition.
Shaded cells are not used by BOR.
Note 1:
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.