Microchip Technology MCP1631RD-MCC2 Data Sheet
2006-2012 Microchip Technology Inc.
DS41291G-page 37
PIC16F882/883/884/886/887
2.2.2.7
PIR2 Register
.
REGISTER DEFINITIONS: PIR2
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-7:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
OSFIF
C2IF
C1IF
EEIF
BCLIF
ULPWUIF
—
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6
C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 5
C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 4
EEIF: EE Write Operation Interrupt Flag bit
1 = Write operation completed (must be cleared in software)
0 = Write operation has not completed or has not started
1 = Write operation completed (must be cleared in software)
0 = Write operation has not completed or has not started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the MSSP when configured for I
1 = A bus collision has occurred in the MSSP when configured for I
2
C Master mode
0 = No bus collision has occurred
bit 2
ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag bit
1 = Wake-up condition has occurred (must be cleared in software)
0 = No Wake-up condition has occurred
1 = Wake-up condition has occurred (must be cleared in software)
0 = No Wake-up condition has occurred
bit 1
Unimplemented: Read as ‘0’
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode