Intel Core™ 2 Duo U7600 U7600 User Manual

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 Specification 

Update 

Workaround: It is possible for the BIOS to contain a workaround for this erratum. 

For the steppings affected, see the Summary Tables of Changes. 

IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to indicate 

whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at the time of the 

last update to the IA32_MC1_STATUS MSR.  Due to this erratum, IA32_MC1_STATUS 

MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit. 

Implication:  IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the enable bit in 

the IA32_MC1_CTL MSR at the time of the last update.  

Workaround: None identified. 

For the steppings affected, see the Summary Tables of Changes. 

A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints 

until after execution of the following instruction. This is intended to allow the 

sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without 

having an invalid stack during interrupt handling. However, an enabled debug 

breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is 

followed by an instruction that signals a floating point exception rather than a MOV 

[r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an 

unexpected instruction boundary since the MOV SS/POP SS and the following 

instruction should be executed atomically. 

Implication:  This can result in incorrect signaling of a debug exception and possibly a mismatched 

Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV 

[r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on 

any exception. Intel has not observed this erratum with any commercially available 

software, or system.  

Workaround: As recommended in the IA32 Intel® Architecture Software Developer’s Manual, the 

use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure 

since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers 

of debug tools should be aware of the potential incorrect debug event signaling 

created by this erratum. 

For the steppings affected, see the Summary Tables of Changes.