Intel Core™ 2 Duo U7600 U7600 User Manual

Product codes
U7600
Page of 42
 
Errata 
 
 
Specification Update 
 39 
AZ56. 
Code Segment Limit/Canonical Faults on RSM May be Serviced before 
Higher Priority Interrupts/Exceptions and May Push the Wrong 
Address Onto the Stack 
Problem: 
Normally, when the processor encounters a Segment Limit or Canonical Fault due to 
code execution, a #GP (General Protection Exception) fault is generated after all 
higher priority Interrupts and exceptions are serviced.  Due to this erratum, if RSM 
(Resume from System Management Mode) returns to execution flow that results in a 
Code Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher 
priority Interrupt or Exception (e.g. NMI (Non-Maskable Interrupt), Debug 
break(#DB), Machine Check (#MC), etc.). If the RSM attempts to return to a non-
canonical address, the address pushed onto the stack for this #GP fault may not 
match the non-canonical address that caused the fault. 
Implication:  Operating systems may observe a #GP fault being serviced before higher priority 
Interrupts and Exceptions.  Intel has not observed this erratum on any commercially 
available software.  
Workaround: None identified. 
Status: 
For the steppings affected, see the Summary Tables of Changes. 
 
 
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