Microchip Technology MCP3421DM-WS Data Sheet

DS39632E-page 10

 

© 2009 Microchip Technology Inc.

Data Latch

Data Memory

(2 Kbytes)

Address Latch

Data Address<12>

12

Access

BSR

4

4

PCH    PCL

    

 

PCLATH

8

31 Level Stack

Program Counter

PRODL

PRODH

8 x 8 Multiply

8

8

8

ALU<8>

Address Latch

Program Memory

(24/32 Kbytes)

Data Latch

20

8

8

Table Pointer<21>

inc/dec logic

21

8

Table Latch

8

IR

12

3

ROM Latch

PCLATU

PCU

PORTE

MCLR/V

PP

/RE3

RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.

RB3 is the alternate pin for CCP2 multiplexing.

W

STKPTR

Bank

8

8

8

BITOP

FSR0
FSR1
FSR2

inc/dec

Address

12

Decode

logic

EUSART

Comparator

MSSP

10-Bit

 

ADC

Timer2

Timer1

Timer3

Timer0

HLVD

CCP2

BOR

Data

EEPROM

USB

Instruction

Decode &

Control

State Machine
Control Signals

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

OSC2

V

DD

,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Reference

Band Gap

V

SS

MCLR

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

USB Voltage

Regulator

V

USB

PORTB

PORTC

RB0/AN12/INT0/FLT0/SDI/SDA

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2

/UOE

RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO

RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2

/VPO

RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

PORTA

RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT

RA3/AN3/V

REF

+

RA2/AN2/V

REF

-/CV

REF

RA1/AN1

RA0/AN0

OSC2/CLKO/RA6

CCP1