Microchip Technology MCP3421DM-WS Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 124
© 2009 Microchip Technology Inc.
TABLE 10-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTD
(3)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
LATD
(3)
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
TRISD
(3)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
PORTE
RDPU
(3)
—
—
—
RE3
(1,2)
RE2
(3)
RE1
(3)
RE0
(3)
CCP1CON
P1M1
(3)
P1M0
(3)
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
SPPCON
(3)
—
—
—
—
—
—
SPPOWN
SPPEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.