Microchip Technology MCP3421DM-WS Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 126
© 2009 Microchip Technology Inc.
TABLE 10-9:
PORTE I/O SUMMARY
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin
Function
TRIS
Setting
I/O
I/O Type
Description
RE0/AN5/
CK1SPP
CK1SPP
RE0
0
OUT
DIG
LATE<0> data output; not affected by analog input.
1
IN
ST
PORTE<0> data input; disabled when analog input enabled.
AN5
1
IN
ANA
A/D Input Channel 5; default configuration on POR.
CK1SPP
0
OUT
DIG
SPP clock 1 output (SPP enabled).
RE1/AN6/
CK2SPP
CK2SPP
RE1
0
OUT
DIG
LATE<1> data output; not affected by analog input.
1
IN
ST
PORTE<1> data input; disabled when analog input enabled.
AN6
1
IN
ANA
A/D Input Channel 6; default configuration on POR.
CK2SPP
0
OUT
DIG
SPP clock 2 output (SPP enabled).
RE2/AN7/
OESPP
OESPP
RE2
0
OUT
DIG
LATE<2> data output; not affected by analog input.
1
IN
ST
PORTE<2> data input; disabled when analog input enabled.
AN7
1
IN
ANA
A/D Input Channel 7; default configuration on POR.
OESPP
0
OUT
DIG
SPP enable output (SPP enabled).
MCLR/V
PP
/
RE3
MCLR
—
(1)
IN
ST
External Master Clear input; enabled when MCLRE Configuration bit
is set.
is set.
V
PP
—
(1)
IN
ANA
High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
Always available regardless of pin mode.
RE3
—
(1)
IN
ST
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
clear.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input
Note 1:
RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTE
RDPU
(3)
—
—
—
RE3
(1,2)
RE2
(3)
RE1
(3)
RE0
(3)
LATE
(3)
—
—
—
—
—
LATE2
LATE1
LATE0
TRISE
(3)
—
—
—
—
—
TRISE2
TRISE1
TRISE0
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
SPPCON
(3)
—
—
—
—
—
—
SPPOWN
SPPEN
SPPCFG
(3)
CLKCFG1 CLKCFG0
CSEN
CLK1EN
WS3
WS2
WS1
WS0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers or bits are unimplemented on 28-pin devices.