Microchip Technology MCP3421DM-WS Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 267
PIC18F2455/2550/4455/4550
REGISTER 21-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
1 = Right justified
0 = Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 T
111 = 20 T
AD
110 = 16 T
AD
101 = 12 T
AD
100 = 8 T
AD
011 = 6 T
AD
010 = 4 T
AD
001 = 2 T
AD
000 = 0 T
AD(1)
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = F
111 = F
RC
(clock derived from A/D RC oscillator)
(1)
110 = F
OSC
/64
101 = F
OSC
/16
100 = F
OSC
/4
011 = F
RC
(clock derived from A/D RC oscillator)
(1)
010 = F
OSC
/32
001 = F
OSC
/8
000 = F
OSC
/2
Note 1:
If the A/D F
RC
clock source is selected, a delay of one T
CY
(instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.