Microchip Technology MCP3421DM-WS Data Sheet

Page of 438
© 2009 Microchip Technology Inc.
 
DS39632E-page 269
PIC18F2455/2550/4455/4550
The value in the ADRESH:ADRESL registers is
unknown following POR and BOR Resets and is not
affected by any other Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 21.1
“A/D Acquisition Requirements”
. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to perform an
A/D conversion:
1.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
• Clear ADIF bit 
• Set ADIE bit 
• Set GIE bit 
3.
Wait the required acquisition time (if required).
4.
Start conversion:
• Set GO/DONE bit (ADCON0 register)
5.
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6.
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
7.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as T
AD
. A minimum wait of 3 T
AD
 is
required before the next acquisition starts.
FIGURE 21-2:
A/D TRANSFER FUNCTION
FIGURE 21-3:
ANALOG INPUT MODEL 
        
       
D
ig
ital
 C
o
de
 Out
put
3FEh
003h
002h
001h
000h
0.5
 LS
B
1 L
S
B
1.5
 LS
B
2 L
S
B
2.5
 LS
B
1
022
 LS
B
10
22.5
 LS
B
3 L
S
B
Analog Input Voltage
3FFh
1
023
 LS
B
10
23.5
 LS
B
V
AIN
C
PIN
Rs
ANx
5 pF
V
T
 = 0.6V
V
T
 = 0.6V
I
LEAKAGE
R
IC
 ≤ 1k
Sampling
Switch
SS
R
SS
C
HOLD
 = 25 pF
V
SS
V
DD
±100 nA
Legend: C
PIN
V
T
I
LEAKAGE
R
IC
SS
C
HOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/hold Capacitance (from DAC)
various junctions
= Sampling Switch Resistance
R
SS
V
DD
6V
Sampling Switch
5V
4V
3V
2V
1
2
3
4
(k
Ω)