Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 141
PIC18FXX8
16.5.8
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
the ECCP1 module for PWM operation:
1.
Configure the PWM module:
a)
Disable the ECCP1/P1A, P1B, P1C and/or
P1D outputs by setting the respective TRISD
bits.
P1D outputs by setting the respective TRISD
bits.
b)
Set the PWM period by loading the PR2
register.
register.
c)
Set the PWM duty cycle by loading the
ECCPR1L register and ECCP1CON<5:4>
bits.
ECCPR1L register and ECCP1CON<5:4>
bits.
d)
Configure the ECCP1 module for the
desired PWM operation by loading the
ECCP1CON register with the appropriate
value. With the ECCP1M<3:0> bits, select
the active-high/low levels for each PWM
output. With the EPWM1M<1:0> bits, select
one of the available output modes.
desired PWM operation by loading the
ECCP1CON register with the appropriate
value. With the ECCP1M<3:0> bits, select
the active-high/low levels for each PWM
output. With the EPWM1M<1:0> bits, select
one of the available output modes.
e)
For Half-Bridge Output mode, set the dead-
band delay by loading the ECCP1DEL
register with the appropriate value.
band delay by loading the ECCP1DEL
register with the appropriate value.
2.
Configure and start TMR2:
a)
Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
the TMR2IF bit in the PIR1 register.
b)
Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
T2CKPS bits (T2CON<1:0>).
c)
Enable Timer2 by setting the TMR2ON bit
(T2CON<2>) register.
(T2CON<2>) register.
3.
Enable PWM outputs after a new cycle has
started:
started:
a)
Wait until TMR2 overflows (TMR2IF bit
becomes a ‘1’). The new PWM cycle begins
here.
becomes a ‘1’). The new PWM cycle begins
here.
b)
Enable the ECCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISD bits.
P1D pin outputs by clearing the respective
TRISD bits.
TABLE 16-5:
REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
all other
Resets
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
RCON
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 110q 0--0 011q
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
ECCP1IP -1-1 1111 -1-1 1111
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
ECCP1IF -0-0 0000 -0-0 0000
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
ECCP1IE -0-0 0000 -0-0 0000
TMR2
Timer2 Module Register
0000 0000 0000 0000
PR2
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
—
TOUTPS3
TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
ECCPR1H
Enhanced Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
ECCPR1L
Enhanced Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx uuuu uuuu
ECCP1CON EPWM1M1 EPWM1M0
EDC1B1
EDC1B0
ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 0000 0000
ECCPAS
ECCPASE
ECCPAS2
ECCPAS1 ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0 0000 0000 0000 0000
ECCP1DEL
EPDC7
EPDC6
EPDC5
EPDC4
EPDC3
EPDC2
EPDC1
EPDC0
0000 0000 uuuu uuuu
Legend:
x
= unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module.