Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 149
PIC18FXX8
17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep. Before enabling the module in SPI Slave
mode, the clock line must match the proper Idle state.
The clock line can be observed by reading the SCK pin.
The Idle state is determined by the CKP bit
(SSPCON1<4>).
data. When a byte is received, the device will wake-up
from Sleep. Before enabling the module in SPI Slave
mode, the clock line must match the proper Idle state.
The clock line can be observed by reading the SCK pin.
The Idle state is determined by the CKP bit
(SSPCON1<4>).
17.3.7
SLAVE SELECT
SYNCHRONIZATION
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The data latch
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The data latch
must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
may be desirable depending on the application.
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
may be desirable depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 17-4:
SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> = 0100),
the SPI module will reset if the SS pin is set
to V
the SPI module will reset if the SS pin is set
to V
DD
.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
enabled.
SCK
(CKP = 1
(CKP = 1
SCK
(CKP = 0
(CKP = 0
Input
Sample
Sample
SDI
bit 7
SDO
bit 7
bit 6
bit 7
SSPIF
Interrupt
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPBUF
SSPSR to
SSPBUF
SSPBUF
SS
Flag
bit 0
bit 7
bit 0
Next Q4 cycle
after Q2
after Q2
↓