Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 155
PIC18FXX8
REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I
2
C MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (Slave mode only)
1
= Enable interrupt when a general call address (0000h) is received in the SSPSR
0
= General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1
= Acknowledge was not received from slave
0
= Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)
1
= Not Acknowledge
0
= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1
= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0
= Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master Mode only)
1
= Enables Receive mode for I
2
C
0
= Receive Idle
bit 2
PEN: Stop Condition Enable bit (Master mode only)
1
= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit (Master mode only)
1
= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Repeated Start condition Idle
bit 0
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1
1
= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Start condition Idle
In Slave mode:
1
1
= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0
= Clock stretching is enabled for slave transmit only (Legacy mode)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
2
C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
to the SSPBUF are disabled).