Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 185
PIC18FXX8
18.1
USART Baud Rate Generator
(BRG)
(BRG)
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running, 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA register) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 18-1 shows the formula for
computation of the baud rate for different USART
modes which only apply in Master mode (internal
clock).
Synchronous modes of the USART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running, 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA register) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 18-1 shows the formula for
computation of the baud rate for different USART
modes which only apply in Master mode (internal
clock).
Given the desired baud rate and F
OSC
, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
using the formula in Table 18-1. From this, the error in
baud rate can be determined.
Example 18-1 shows the calculation of the baud rate
error for the following conditions:
error for the following conditions:
F
OSC
= 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the F
(BRGH = 1) even for slower baud clocks. This is
because the F
OSC
/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
18.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 18-1:
CALCULATING BAUD RATE ERROR
TABLE 18-1:
BAUD RATE FORMULA
TABLE 18-2:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Desired Baud Rate
= F
OSC
/(64 (X + 1))
Solving for X:
X
= ((F
OSC
/Desired Baud Rate)/64) – 1
X
= ((16000000/9600)/64) – 1
X
= [25.042] = 25
Calculated Baud Rate
= 16000000/(64 (25 + 1))
= 9615
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
= 0.16%
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = F
OSC
/(64 (X + 1))
(Synchronous) Baud Rate = F
OSC
/(4 (X + 1))
Baud Rate = F
OSC
/(16 (X + 1))
NA
Legend: X = value in SPBRG (0 to 255)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000u
SPBRG
Baud Rate Generator Register
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.