Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 19
PIC18FXX8
2.4
External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from Sleep mode.
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-3:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
OPERATION (EC OSC
CONFIGURATION)
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. Figure 2-4 shows the pin
connections for the ECIO Oscillator mode.
except that the OSC2 pin becomes an additional
general purpose I/O pin. Figure 2-4 shows the pin
connections for the ECIO Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION (ECIO
CONFIGURATION)
OPERATION (ECIO
CONFIGURATION)
2.5
HS4 (PLL)
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
mable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
The PLL can only be enabled when the oscillator
configuration bits are programmed for HS mode. If they
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
configuration bits are programmed for HS mode. If they
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC2:FOSC0
configuration bits. The oscillator mode is specified
during device programming.
configuration bits. The oscillator mode is specified
during device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out referred to as T
locked before device execution starts. The PLL lock
timer has a time-out referred to as T
PLL
.
FIGURE 2-5:
PLL BLOCK DIAGRAM
OSC1
OSC2
F
OSC
/4
Clock from
Ext. System
Ext. System
PIC18FXX8
OSC1
I/O (OSC2)
Clock from
Ext. System
Ext. System
PIC18FXX8
MU
X
VCO
Loop
Filter
Filter
Divide by 4
Crystal
Osc
OSC2
OSC1
F
IN
F
OUT
SYSCLK
Phase
Comparator
FOSC2:FOSC0 = 110