Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 209
PIC18FXX8
REGISTER 19-10: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS
REGISTER 19-11: TXERRCNT: TRANSMIT ERROR COUNT REGISTER
U-0
R/W-x
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
TXRTR: Transmission Frame Remote Transmission Request bit
1
= Transmitted message will have TXRTR bit set
0
= Transmitted message will have TXRTR bit cleared
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
DLC3:DLC0: Data Length Code bits
1111
= Reserved
1110
= Reserved
1101
= Reserved
1100
= Reserved
1011
= Reserved
1010
= Reserved
1001
= Reserved
1000
= Data Length = 8 bytes
0111
= Data Length = 7 bytes
0110
= Data Length = 6 bytes
0101
= Data Length = 5 bytes
0100
= Data Length = 4 bytes
0011
= Data Length = 3 bytes
0010
= Data Length = 2 bytes
0001
= Data Length = 1 bytes
0000
= Data Length = 0 bytes
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
bit 7
bit 0
bit 7-0
TEC7:TEC0: Transmit Error Counter bits
This register contains a value which is derived from the rate at which errors occur. When the
error count overflows, the bus-off state occurs. When the bus has 128 occurrences of
11 consecutive recessive bits, the counter value is cleared.
error count overflows, the bus-off state occurs. When the bus has 128 occurrences of
11 consecutive recessive bits, the counter value is cleared.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown