Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 235
PIC18FXX8
19.8
Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
Phase Segment 1 and Phase Segment 2, as
necessary. There are two mechanisms used for
synchronization.
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
Phase Segment 1 and Phase Segment 2, as
necessary. There are two mechanisms used for
synchronization.
19.8.1
HARD SYNCHRONIZATION
Hard synchronization is only done when there is a reces-
sive to dominant edge during a bus Idle condition, indi-
cating the start of a message. After hard
synchronization, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge which
has occurred to lie within the synchronization segment of
the restarted bit time. Due to the rules of synchroniza-
tion, if a hard synchronization occurs, there will not be a
resynchronization within that bit time.
sive to dominant edge during a bus Idle condition, indi-
cating the start of a message. After hard
synchronization, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge which
has occurred to lie within the synchronization segment of
the restarted bit time. Due to the rules of synchroniza-
tion, if a hard synchronization occurs, there will not be a
resynchronization within that bit time.
19.8.2
RESYNCHRONIZATION
As a result of resynchronization, Phase Segment 1
may be lengthened or Phase Segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure 19-8) or subtracted from Phase Segment 2 (see
Figure 19-9). The SJW is programmable between 1 T
may be lengthened or Phase Segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure 19-8) or subtracted from Phase Segment 2 (see
Figure 19-9). The SJW is programmable between 1 T
Q
and 4 T
Q
.
Clocking information will only be derived from reces-
sive to dominant transitions. The property, that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
sive to dominant transitions. The property, that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
The phase error of an edge is given by the position of
the edge relative to Sync_Seg, measured in T
the edge relative to Sync_Seg, measured in T
Q
. The
phase error is defined in magnitude of T
Q
as follows:
• e = 0 if the edge lies within Sync_Seg.
• e > 0 if the edge lies before the sample point.
• e < 0 if the edge lies after the sample point of the
previous bit.
If the magnitude of the phase error is less than or equal
to the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
to the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
If the magnitude of the phase error is larger than the
synchronization jump width and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the synchronization jump width.
synchronization jump width and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the synchronization jump width.
If the magnitude of the phase error is larger than the
resynchronization jump width and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the synchronization jump width.
resynchronization jump width and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the synchronization jump width.
19.8.3
SYNCHRONIZATION RULES
• Only one synchronization within one bit time is
allowed.
• An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
(previously read bus value) differs from the bus
value immediately after the edge.
• All other recessive to dominant edges, fulfilling
rules 1 and 2, will be used for resynchronization
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
FIGURE 19-8:
LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)
Input
Sync
Prop
Segment
Phase
Segment 1
Phase
Segment 2
≤ SJW
Sample Point
T
Q
Signal
Nominal Bit Length
Actual Bit Length
Bit
Time
Segments
Time
Segments