Microchip Technology DM164134 Data Sheet
© 2006 Microchip Technology Inc.
DS41159E-page 239
PIC18FXX8
TABLE 19-3:
VALUES FOR ICODE<2:0>
19.13.4
MESSAGE ERROR INTERRUPT
When an error occurs during transmission or reception
of a message, the message error flag IRXIF will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
of a message, the message error flag IRXIF will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
19.13.5
BUS ACTIVITY WAKE-UP
INTERRUPT
INTERRUPT
When the PIC18FXX8 is in Sleep mode and the bus
activity wake-up interrupt is enabled, an interrupt will be
generated and the WAKIF bit will be set when activity is
detected on the CAN bus. This interrupt causes the
PIC18FXX8 to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
activity wake-up interrupt is enabled, an interrupt will be
generated and the WAKIF bit will be set when activity is
detected on the CAN bus. This interrupt causes the
PIC18FXX8 to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
19.13.6
ERROR INTERRUPT
When the error interrupt is enabled, an interrupt is
generated if an overflow condition occurs or if the error
state of transmitter or receiver has changed. The error
flags in COMSTAT will indicate one of the following
conditions.
generated if an overflow condition occurs or if the error
state of transmitter or receiver has changed. The error
flags in COMSTAT will indicate one of the following
conditions.
19.13.6.1
Receiver Overflow
An overflow condition occurs when the MAB has
assembled a valid received message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
COMSTAT.RXnOVFL bit will be set to indicate the
overflow condition. This bit must be cleared by the
MCU.
assembled a valid received message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
COMSTAT.RXnOVFL bit will be set to indicate the
overflow condition. This bit must be cleared by the
MCU.
19.13.6.2
Receiver Warning
The receive error counter has reached the MCU
warning limit of 96.
warning limit of 96.
19.13.6.3
Transmitter Warning
The transmit error counter has reached the MCU
warning limit of 96.
warning limit of 96.
19.13.6.4
Receiver Bus Passive
The receive error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
passive limit of 127 and the device has gone to
error-passive state.
19.13.6.5
Transmitter Bus Passive
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
passive limit of 127 and the device has gone to
error-passive state.
19.13.6.6
Bus-Off
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
device has gone to bus-off state.
19.13.7
INTERRUPT ACKNOWLEDGE
Interrupts are directly associated with one or more
status flags in the PIR register. Interrupts are pending
as long as one of the flags is set. Once an interrupt flag
is set by the device, the flag cannot be reset by the
microcontroller until the interrupt condition is removed.
status flags in the PIR register. Interrupts are pending
as long as one of the flags is set. Once an interrupt flag
is set by the device, the flag cannot be reset by the
microcontroller until the interrupt condition is removed.
ICOD
<2:0>
Interrupt
Boolean Expression
000
None
ERR•WAK•TX0•TX1•TX2•RX0•
RX1
RX1
001
Error
ERR
010
TXB2
ERR•TX0•TX1•TX2
011
TXB1
ERR•TX0•TX1
100
TXB0
ERR•TX0
101
RXB1
ERR•TX0•TX1•TX2•RX0•RX1
110
RXB0
ERR•TX0•TX1•TX2•RX0
111
Wake on
Interrupt
ERR•TX0•TX1•TX2•RX0•RX1•
WAK
WAK
Key:
ERR = ERRIF * ERRIE
ERR = ERRIF * ERRIE
RX0 = RXB0IF * RXB0IE
TX0 = TXB0IF * TXB0IE
RX1 = RXB1IF * RXB1IE
TX1 = TXB1IF * TXB1IE
WAK = WAKIF * WAKIE
TX2 = TXB2IF * TXB2IE